As known, the internal buses of the computer system in the early stage include an advanced graphic port (AGP) bus and a peripheral component Interconnect (PCI) bus. The AGP bus is connected with a graphic card. The PCI bus is connected with a peripheral device such as an internet card.
Since the data transmission speed of a PCI Express (PCIe) bus is fast, the conventional AGP bus and the conventional PCI bus are replaced by the PCIe bus. In other words, the internal devices of the computer system are all connected with the PCIe buses.
For example, the graphic card and the solid state drive (SSD) of the existing computer system are connected with the PCIe buses.
FIG. 1 is a schematic block diagram illustrating the connection between a solid state drive and a host of a conventional computer system. The solid state drive 100 is connected with the host 130 through a PCIe bus 120.
Moreover, the solid state drive 100 comprises a controlling circuit 110 and a flash array 105. The controlling circuit 110 is connected with the flash array 105.
The controlling circuit 110 comprises a PCIe physical layer circuit 112, which is also referred as a PCIe PHY circuit. The host 130 comprises a PCIe physical layer circuit 132. The PCIe physical layer circuit 112 of the controlling circuit 110 and the PCIe physical layer circuit 132 of the host 130 are connected with each other through the PCIe bus 120.
Consequently, the host 130 may issue an access command to the controlling circuit 110 of the solid state drive 100 through the PCIe bus 120. For example, according to a write command, a write data from the host 130 is stored into the flash array 105 under control of the controlling circuit 110. Alternatively, according to a read command, a read data is read from the flash array 105 and transmitted to the host 130 under control of the controlling circuit 110.
According to the specifications of the PCIe bus 120, one of plural control signals from the PCIe bus 120 is a reset signal. As shown in FIG. 1, the PCIe physical layer circuit 132 of the host 130 has a reset terminal RESET1# to activate the reset signal. Moreover, the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 is connected with a reset terminal RESET2# of the PCIe physical layer circuit 112 of the controlling circuit 110 through a physical wire. Consequently, the PCIe physical layer circuit 132 of the host 130 can activate the reset signal through the reset terminal RESET1# at any time and directly reset the PCIe physical layer circuit 112 of the controlling circuit 110.
According to the specifications of the PCIe bus 120, the reset signal of the PCIe bus 120 has the highest priority to be processed. That is, when the reset terminal RESET2# of the PCIe physical layer circuit 112 of the controlling circuit 110 receives the reset signal, the PCIe physical layer circuit 112 of the controlling circuit 110 has to be reset immediately. Generally, the PCIe physical layer circuit 132 of the host 130 can activate the reset signal at any time. If the host 130 activates the reset signal while the PCIe physical layer circuit 112 of the controlling circuit 110 is executing the access command, the PCIe physical layer circuit 112 of the controlling circuit 110 is reset compulsively. Consequently, the data that is being processed by the controlling circuit 110 is possibly suffered from corruption. Under this circumstance, the solid state drive 100 is suffered from unrecoverable injury.